Hironori Uchikawa
Ph.D. (Engineering)
Chief Specialist
System Technology Research & Development Center
Institute of Memory Technology R&D
Kioxia Corporation (formerly known as Toshiba Memory)
E-mail: gotz <at> ieee <dot> org
Summary
Hironori Uchikawa was born in Kanagawa, Japan in 1978. He received the B.E. and M.E. degrees in electrical engineering from Yokohama National University in 2001 and 2003 respectively. He received the Ph.D. degree in electrical engineering from Tokyo Institute of Technology in 2012. In 2003, he joined the Research and Development Center at Toshiba Corp. where he was engaged in research on MIMO-OFDM systems, especially for the IEEE 802.11n standard. Also, he developed error-correcting codes, especially low-density parity check (LDPC) codes, for NAND flash memory systems. Since 2013, he had been a Visiting Scholar in the Center for Memory Recording Research (CMRR) at University of California, San Diego and engaged in research on coding for distributed storage systems and flash memories. He also developed an FPGA-based platform for experiments of flash memories at the CMRR. He is currently a Senior Specialist in the System Technology Research and Development Center at Kioxia Corporation (formerly known as Toshiba Memory). His research interests include coding theory, information theory, communication theory and their applications to storage systems. He has authored and co-authored 28 international journal papers and conference papers, and he holds 48 U.S. patents. Dr. Uchikawa is a Senior Member of both the IEEE and the Institute of Electronics, Information and Communication Engineers (IEICE) of Japan. He received the 2008 Young Researcher’s Award of the IEICE.
Education
| March 2001 | B.E. in Yokohama National University | Advisor: Prof. Ryuji Kohno |
| March 2003 | M.E. in Yokohama National University | Advisor: Prof. Ryuji Kohno |
| March 2012 | D.E. in Tokyo Institute of Technology | Advisor: Prof. Kohichi Sakaniwa |
Professional Activities
Reviewer for IEICE, IEEE Trans. on IT, Comm., CAS, VLSI Systems, and numerous IEEE conferences.
Vice-Chair from Industry of Data Storage Technical Committee in IEEE ComSoc. (2019-2022)
Program Co-Chair for NVMW2024
TPC member for Globecom2019-2024, ICC2019-2023, NVMW2018-2013, ICNC2013, and Workshop on Coding for Flash Memories 2012.
Guest Associate Editor of Special Section on Information Theory and Its Applications 2013 of IEICE Transactions.
Secretary of ISITA2020.
Associate Editor of IEICE Transactions on Fundamentals of Electronics,
Communications and Computer Sciences (2021)
Area Editor of IEICE Transactions on Fundamentals of Electronics,
Communications and Computer Sciences (2022-Current)
Guest Editor of Special Section on Information Theory and Its Applications 2025 of IEICE Transactions.
Senior Members of both the IEEE and the IEICE.
Honors
2008 Young Researcher’s Award of the IEICE
Publications
Patents
32 Domestic patents, 48 United states patents (Oct. 2022)